Description
This is a basic level course teaching the Systemverilog HDL from beginning. This will cover only the basics of SV and designed for absolute beginners in it. This is suitable for those who plan to learn Verilog HDL as well, as both languages are almost same in beginner level.
If you are an expert, or someone who is already coding in Systemverilog, this course is NOT for you.
This covers below topics in a concise from so that you can quickly start with coding in Verilog or Systemverilog.
    Writing Verilog and Systemverilog “Hello World” kind of programs
    ‘Module’ construct in these languages and its general structure
    Writing first module
    What is design and test-bench coding in an HDL
    Basics of Assignment in Verilog and SV:
    Continuous Assignment
    Procedural Assignment blocks and their usage
    Design and test bench programs for some basic circuits like, adder, alu, multiplexer & counter
    Learning Systemverilog
Who this course is for:
    Beginner Verilog or Systemverilog learners.. This course is not for those who are already familiar with those.
Requirements
    Be familiar with basics of digital circuits and IC design flow
Last updated 12/2018